US11449247B2
Intel Corporation
📅 Filed: 2020-11-19
✅ Granted: 2022-09-20
A multichip package including a main die coupled to transceiver dies. Universal interface blocks configured to interface with on-package memory or on-die tightly-coupled components.
US8165191B2
Altera Corporation
📅 Filed: 2008-10-17
✅ Granted: 2012-04-24
Multi-gigahertz system interconnect technology supporting chip-to-chip, board-to-board, backplane and box-to-box levels via configurable channel-aggregated transceivers.
US8949493B1
Altera Corporation
📅 Filed: 2010-07-30
✅ Granted: 2015-02-03
Configurable scrambling circuitry supporting multiple protocols. Configurable multilane scrambler adapts through combining scrambling circuits across lanes or operating independently.
US7843216B2
Altera Corporation
📅 Filed: 2008-08-18
✅ Granted: 2010-11-30
Channel alignment for data transmission interfaces in HIP blocks on programmable logic integrated circuits, using reduced parallel data path count to save logic resources.
US11115025B2
Intel Corporation
📅 Filed: 2018-03-29
✅ Granted: 2021-09-07
Modular transceiver-based network circuitry with configurable gaskets that provide transparent interfaces to processing elements, enabling easier system integration.
US9240804B2
Altera Corporation
📅 Filed: 2013-02-05
✅ Granted: 2016-01-19
Receiver circuits in serial lanes generate synchronous clock signals aligned with a master clock for corruption-free synchronous data transfer via serial-to-parallel converters.
US8416903B1
Altera Corporation
📅 Filed: 2011-04-29
✅ Granted: 2013-04-09
DDR circuitry enhanced with edge detection capability using serial training data with successive equal-valued bit pairs, evaluated against differently-phased candidate clock signals.
US8650447B1
Altera Corporation
📅 Filed: 2011-07-14
✅ Granted: 2014-02-11
Precision error injection control via synchronous error signals accompanying data transfers along pipeline stages, enabling targeted error events for testing and validation.
WO2010126679A2
Altera Corporation
📅 Filed: 2010-04-02
📄 Published: 2010-11-04
FPGA-based digital IP strip chip design for embedding configurable logic blocks alongside ASIC functions, enabling hybrid prototype-to-production silicon architectures.
US20190065427A1
Intel Corporation
📅 Filed: 2018-10-31
📄 Published: 2019-02-28
Time-division multiplexing to send two or more protocols over an interconnect bridge between two die — where the first protocol is a down-configured version of a high-bandwidth protocol.
US8458383B1
Altera Corporation
📅 Filed: 2007-08-30
✅ Granted: 2013-06-04
Programmable device interface where each layer of a protocol stack (physical, data link, transaction) is selectably bypassable, allowing partial stack implementations for custom protocols.
US9736086B1
Altera Corporation
📅 Filed: 2011-04-29
✅ Granted: 2017-08-15
Data buffering apparatus with a mode selection input and FIFO circuit operative to buffer data signals between interfaces — supporting multiple protocols in a single configurable hardware block.
US9436250B1
Altera Corporation
📅 Filed: 2011-12-19
✅ Granted: 2016-09-06
Integrated circuit with PMA and PCS communication circuitry, a body bias generator providing adaptive bias to reduce power consumption dynamically under varying load conditions.
US8193953B1
Altera Corporation
📅 Filed: 2010-05-14
✅ Granted: 2012-06-05
Circuitry for scaling data width between first and second widths across a wide range of ratios, including non-integer and non-rational ratios, for flexible bus-width adaptation.
US8901961B1
Altera Corporation
📅 Filed: 2012-11-28
✅ Granted: 2014-12-02
PLD comprising a substrate with arrays of programmable logic elements and columnar interfaces extending parallel to substrate sides, enabling efficient signal routing and rebuffering.
US10216219B1
Altera Corporation
📅 Filed: 2016-11-18
✅ Granted: 2019-02-26
Configurable multi-protocol transceiver with configurable deskew settings for adapting transmit/receive communications to a selected protocol with minimal skew.
US7982639B1
Altera Corporation
📅 Filed: 2009-09-01
✅ Granted: 2011-07-19
Serial data with extra protocol encoding bits partially deserialized using a low-speed clock at varying frequencies, enabling clean conversion from serial to parallel with protocol bits separated.
US7295641B1
Altera Corporation
📅 Filed: 2003-11-26
✅ Granted: 2007-11-13
Accurate approximation of data signal phase relative to a reference clock using only coarse increments of phase shift — reducing circuit complexity for high-speed clock-data recovery.
JP2006166445A
Altera Corporation
📅 Filed: 2005-12-01
📄 Published: 2006-06-22
Technique for capturing output signals from HIP blocks operating at frequencies higher than programmable logic, by frequency-reducing output to enable reliable capture and analysis.
US7801121B1
Altera Corporation
📅 Filed: 2006-04-20
✅ Granted: 2010-09-21
Programmable logic transmitter and receiver circuitry for multi-lane serial links with data packet CRC checking, including priority data packet handling for reliable high-speed communication.